1. Field
This disclosure relates generally to latches, and more specifically, to a state retaining power gated latch and method therefor.
2. Related Art
Lower power consumption has been gaining importance in integrated circuit data processing systems due to, for example, wide spread use of portable and handheld applications. Most circuits in handheld devices are typically off (e.g., in an idle or deep sleep mode) for a significant portion of time, consuming only leakage power. As transistor leakage currents increase with finer geometry manufacturing processes, it becomes more difficult to meet chip leakage targets using traditional power reduction techniques. Therefore, reducing leakage current is becoming an increasingly important factor in extending battery life.
One method that has been used to reduce leakage current of integrated circuits is to increase the threshold voltage of the transistors in the device. However, simply increasing the threshold voltage of the transistors may result in unwanted consequences such as slowing the operating speed of the device and limiting circuit performance. Typically, a lower leakage transistor is formed using a relatively thicker gate dielectric and/or an increased channel length.
Another method that has been used to reduce leakage current is to “power gate”, or cut off power to certain blocks of the integrated circuit that are not needed when the device is in a low power mode. However, in doing so, the state of the circuit block is lost. One or more state retention circuits are used to prevent loss of important information and allow for proper circuit operation and performance when recovering from a low power mode. A typical state retention circuit includes a latch circuit implemented using low leakage transistors. During a low power mode, the last logic state before power down is retained in one or more of the latch circuits while the rest of the integrated circuit is powered down. To further reduce power consumption, the power supply voltage to the state retention latch circuit may be lowered. When normal operation is resumed, the logic state of the state retention latch is used to recover the system state.
During normal operation, the state retention latch functions as a normal latch. However, because the state retention latch is implemented with lower leakage transistors, the state retention latch requires a relatively longer setup time. A setup time of a latch is the minimal amount of time required to change the logic state stored in the latch. The relatively long setup time can limit the operating frequency of the integrated circuit.
Therefore, what is needed is a state retention latch that solves the above problems.